//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-31968024
// Cuda compilation tools, release 12.0, V12.0.76
// Based on NVVM 7.0.1
//

.version 8.0
.target sm_52
.address_size 64

.const .align 16 .b8 params[384];

.visible .func  (.param .align 8 .b8 func_retval0[32]) __direct_callable__oxMain(
	.param .b32 __direct_callable__oxMain_param_0,
	.param .align 8 .b8 __direct_callable__oxMain_param_1[8]
)
{
	.reg .pred 	%p<9>;
	.reg .b16 	%rs<41>;
	.reg .f32 	%f<136>;
	.reg .b32 	%r<32>;
	.reg .b64 	%rd<48>;


	ld.param.u32 	%r3, [__direct_callable__oxMain_param_0];
	ld.param.f32 	%f1, [__direct_callable__oxMain_param_1];
	ld.param.f32 	%f2, [__direct_callable__oxMain_param_1+4];
	ld.const.u64 	%rd8, [params+8];
	cvta.to.global.u64 	%rd9, %rd8;
	mul.wide.u32 	%rd10, %r3, 12;
	add.s64 	%rd11, %rd9, %rd10;
	ld.global.s32 	%rd1, [%rd11];
	ld.global.s32 	%rd2, [%rd11+4];
	ld.global.s32 	%rd3, [%rd11+8];
	ld.const.u32 	%r1, [params+16];
	setp.gt.u32 	%p1, %r1, %r3;
	@%p1 bra 	$L__BB0_4;
	bra.uni 	$L__BB0_1;

$L__BB0_4:
	mov.f32 	%f126, 0f3F800000;
	bra.uni 	$L__BB0_5;

$L__BB0_1:
	sub.s32 	%r4, %r3, %r1;
	ld.const.u64 	%rd12, [params+32];
	cvta.to.global.u64 	%rd13, %rd12;
	mul.wide.u32 	%rd14, %r4, 4;
	add.s64 	%rd15, %rd13, %rd14;
	ld.const.u64 	%rd16, [params+24];
	cvta.to.global.u64 	%rd17, %rd16;
	shl.b64 	%rd18, %rd1, 3;
	add.s64 	%rd19, %rd17, %rd18;
	ld.global.v2.f32 	{%f36, %f37}, [%rd19];
	shl.b64 	%rd20, %rd2, 3;
	add.s64 	%rd21, %rd17, %rd20;
	ld.global.v2.f32 	{%f40, %f41}, [%rd21];
	shl.b64 	%rd22, %rd3, 3;
	add.s64 	%rd23, %rd17, %rd22;
	ld.global.v2.f32 	{%f44, %f45}, [%rd23];
	mov.f32 	%f48, 0f3F800000;
	sub.f32 	%f49, %f48, %f1;
	sub.f32 	%f50, %f49, %f2;
	mul.f32 	%f51, %f1, %f40;
	mul.f32 	%f52, %f1, %f41;
	fma.rn.f32 	%f53, %f50, %f36, %f51;
	fma.rn.f32 	%f54, %f50, %f37, %f52;
	fma.rn.f32 	%f3, %f2, %f44, %f53;
	fma.rn.f32 	%f4, %f2, %f45, %f54;
	ld.global.u32 	%r2, [%rd15];
	and.b32  	%r5, %r2, -16384;
	setp.eq.s32 	%p2, %r5, 16384;
	@%p2 bra 	$L__BB0_3;
	bra.uni 	$L__BB0_2;

$L__BB0_3:
	add.s32 	%r17, %r2, -16384;
	ld.const.u64 	%rd32, [params+48];
	cvta.to.global.u64 	%rd33, %rd32;
	mul.wide.u32 	%rd34, %r17, 8;
	add.s64 	%rd35, %rd33, %rd34;
	ld.global.u64 	%rd36, [%rd35];
	tex.2d.v4.f32.f32 	{%f65, %f66, %f67, %f68}, [%rd36, {%f3, %f4}];
	cvt.sat.f32.f32 	%f69, %f65;
	mul.f32 	%f70, %f69, 0f437F0000;
	cvt.rzi.s32.f32 	%r18, %f70;
	cvt.sat.f32.f32 	%f71, %f66;
	mul.f32 	%f72, %f71, 0f437F0000;
	cvt.rzi.s32.f32 	%r19, %f72;
	cvt.sat.f32.f32 	%f73, %f67;
	mul.f32 	%f74, %f73, 0f437F0000;
	cvt.rzi.s32.f32 	%r20, %f74;
	shl.b32 	%r21, %r19, 8;
	or.b32  	%r22, %r21, %r18;
	shl.b32 	%r23, %r20, 16;
	or.b32  	%r24, %r22, %r23;
	not.b32 	%r25, %r24;
	cvt.rn.f32.s32 	%f126, %r25;
	bra.uni 	$L__BB0_12;

$L__BB0_2:
	abs.f32 	%f55, %f3;
	cvt.rmi.f32.f32 	%f56, %f55;
	sub.f32 	%f57, %f55, %f56;
	abs.f32 	%f58, %f4;
	cvt.rmi.f32.f32 	%f59, %f58;
	sub.f32 	%f60, %f58, %f59;
	ld.const.u64 	%rd24, [params+40];
	cvta.to.global.u64 	%rd25, %rd24;
	shl.b32 	%r6, %r2, 4;
	cvt.u64.u32 	%rd26, %r6;
	and.b64  	%rd27, %rd26, 1048560;
	add.s64 	%rd28, %rd25, %rd27;
	ld.global.v2.u32 	{%r7, %r8}, [%rd28];
	cvt.rn.f32.u32 	%f61, %r7;
	mul.f32 	%f62, %f57, %f61;
	cvt.rzi.u32.f32 	%r11, %f62;
	cvt.rn.f32.u32 	%f63, %r8;
	mul.f32 	%f64, %f60, %f63;
	cvt.rzi.u32.f32 	%r12, %f64;
	mad.lo.s32 	%r13, %r7, %r12, %r11;
	cvt.u64.u32 	%rd29, %r13;
	ld.global.u64 	%rd30, [%rd28+8];
	add.s64 	%rd31, %rd30, %rd29;
	ld.u8 	%r14, [%rd31];
	shr.u32 	%r15, %r2, 16;
	and.b32  	%r16, %r15, %r14;
	setp.eq.s32 	%p3, %r16, 0;
	selp.f32 	%f126, 0f00000000, 0f3F800000, %p3;

$L__BB0_5:
	cvt.u32.u64 	%r26, %rd1;
	ld.const.u64 	%rd37, [params];
	cvta.to.global.u64 	%rd4, %rd37;
	mul.wide.s32 	%rd38, %r26, 32;
	add.s64 	%rd39, %rd4, %rd38;
	add.s64 	%rd5, %rd39, 24;
	ld.global.v2.f32 	{%f133, %f82}, [%rd39+24];
	setp.geu.f32 	%p4, %f133, 0f00000000;
	ld.const.u32 	%r27, [params+340];
	setp.ne.s32 	%p5, %r27, 0;
	or.pred  	%p6, %p4, %p5;
	@%p6 bra 	$L__BB0_8;

	div.rn.f32 	%f83, %f133, 0f41200000;
	cvt.rzi.s32.f32 	%r28, %f83;
	neg.s32 	%r29, %r28;
	ld.const.u64 	%rd40, [params+224];
	cvta.to.global.u64 	%rd41, %rd40;
	mul.wide.s32 	%rd42, %r29, 16;
	add.s64 	%rd43, %rd41, %rd42;
	ld.global.f32 	%f84, [%rd43+8];
	setp.geu.f32 	%p7, %f84, 0f00000000;
	@%p7 bra 	$L__BB0_8;

	mov.f32 	%f126, 0f00000000;

$L__BB0_8:
	cvt.u32.u64 	%r30, %rd2;
	mul.wide.s32 	%rd44, %r30, 32;
	add.s64 	%rd45, %rd4, %rd44;
	add.s64 	%rd6, %rd45, 24;
	cvt.u32.u64 	%r31, %rd3;
	mul.wide.s32 	%rd46, %r31, 32;
	add.s64 	%rd47, %rd4, %rd46;
	add.s64 	%rd7, %rd47, 24;
	setp.lt.f32 	%p8, %f82, 0f00000000;
	@%p8 bra 	$L__BB0_10;
	bra.uni 	$L__BB0_9;

$L__BB0_10:
	add.f32 	%f134, %f82, 0f3F800000;
	mov.f32 	%f100, 0f3F800000;
	sub.f32 	%f101, %f100, %f1;
	sub.f32 	%f127, %f101, %f2;
	bra.uni 	$L__BB0_11;

$L__BB0_9:
	ld.global.v2.f32 	{%f86, %f87}, [%rd6];
	ld.global.v2.f32 	{%f88, %f89}, [%rd7];
	mov.f32 	%f91, 0f3F800000;
	sub.f32 	%f92, %f91, %f1;
	sub.f32 	%f127, %f92, %f2;
	mul.f32 	%f93, %f1, %f86;
	mul.f32 	%f95, %f1, %f87;
	fma.rn.f32 	%f96, %f127, %f133, %f93;
	fma.rn.f32 	%f97, %f127, %f82, %f95;
	fma.rn.f32 	%f133, %f2, %f88, %f96;
	fma.rn.f32 	%f134, %f2, %f89, %f97;

$L__BB0_11:
	ld.global.f32 	%f102, [%rd5+-12];
	ld.global.f32 	%f103, [%rd5+-8];
	ld.global.f32 	%f104, [%rd5+-4];
	ld.global.f32 	%f105, [%rd6+-12];
	mul.f32 	%f106, %f1, %f105;
	ld.global.f32 	%f107, [%rd6+-8];
	mul.f32 	%f108, %f1, %f107;
	ld.global.f32 	%f109, [%rd6+-4];
	mul.f32 	%f110, %f1, %f109;
	fma.rn.f32 	%f111, %f127, %f102, %f106;
	fma.rn.f32 	%f112, %f127, %f103, %f108;
	fma.rn.f32 	%f113, %f127, %f104, %f110;
	ld.global.f32 	%f114, [%rd7+-12];
	ld.global.f32 	%f115, [%rd7+-8];
	ld.global.f32 	%f116, [%rd7+-4];
	fma.rn.f32 	%f117, %f2, %f114, %f111;
	fma.rn.f32 	%f118, %f2, %f115, %f112;
	fma.rn.f32 	%f119, %f2, %f116, %f113;
	mul.f32 	%f120, %f118, %f118;
	fma.rn.f32 	%f121, %f117, %f117, %f120;
	fma.rn.f32 	%f122, %f119, %f119, %f121;
	sqrt.rn.f32 	%f123, %f122;
	rcp.rn.f32 	%f124, %f123;
	mul.f32 	%f132, %f119, %f124;
	mul.f32 	%f131, %f118, %f124;
	mul.f32 	%f130, %f117, %f124;

$L__BB0_12:
	st.param.f32 	[func_retval0+0], %f130;
	st.param.f32 	[func_retval0+4], %f131;
	st.param.f32 	[func_retval0+8], %f132;
	st.param.v4.b8 	[func_retval0+12], {%rs17, %rs18, %rs19, %rs20};
	st.param.f32 	[func_retval0+16], %f133;
	st.param.f32 	[func_retval0+20], %f134;
	st.param.f32 	[func_retval0+24], %f126;
	st.param.v4.b8 	[func_retval0+28], {%rs21, %rs22, %rs23, %rs24};
	ret;

}
	// .globl	oxMain
.visible .entry oxMain()
{
	.reg .b64 	%rd<2>;


	mov.u64 	%rd1, __direct_callable__oxMain;
	// begin inline asm
	// end inline asm
	ret;

}

